The invention relates to metal detectors, and more specifically, to target identification circuitry in metal detectors.
Metal detectors typically identify the type of a metal object located in a background environment by analyzing the characteristics of an electrical signal attributable to the target. In particular, some metal detectors identify target type by analyzing the phase relationship between a signal transmitted into the ground and a received signal. For example, some metal detectors use phase detectors, sometimes called xe2x80x9csynchronous detectors,xe2x80x9d to measure the received signal at two different phases, usually 90xc2x0 apart. When the phase detectors are 90xc2x0 apart, they are referred to as being in xe2x80x9cquadrature.xe2x80x9d The output of each of the phase detectors is a D.C. signal proportional to the magnitude of the received signal at a selected phase angle. The ratio between these D.C. signals is proportional to the phase relationship between transmitted and received signals.
Conventional metal detectors analyze the measured ratio by sequentially comparing it to a series of expected ratios. Such detectors compare the measured ratio with a series of expected ratios one by one until they find the best match. Typical digital and microprocessor based systems, for example, sequentially analyze measured phase data by stepping through a pre-defined series of ranges to find a best fit. Often, this approach is expensive to implement, causes switching noise and signal delays, and can be less accurate.
The invention relates to a flash phase circuit and a flash phase analysis method used in a metal detector to evaluate a measured signal relative to two or more preselected phase channels or xe2x80x9cwindowsxe2x80x9d simultaneously. The flash phase analysis circuit provides parallel phase channels for simultaneously analyzing a detected signal in each of several phase windows and providing parallel outputs indicating whether a detected metal target falls in one of the phase windows. To provide the parallel phase channels, the flash phase analysis circuit divides a detected signal among the phase windows. There are a variety of alternative configurations for dividing the detected signal among the phase windows. In one approach, the circuit divides a phase detected signal into signal levels for each phase window. In another approach, the circuit analyzes the detected signal in a phase detector for each phase window in parallel.
To analyze and identify the target type, the circuit simultaneously compares the measured signal at each phase window with a reference signal. The circuit matches measured data with pre-selected phase characteristics corresponding to known targets in parallel and provides parallel output signals indicating target type. The reference signal, in one approach, is a phase detected signal. For example, the selected signal levels of a first phase detected signal are compared with a second phase detected signal. In another approach, the reference signal is a constant reference signal for each phase window.
The analysis circuitry provides a parallel output signal for each phase window indicating which phase window matches with the measured phase data. The parallel output signals can be presented to the user in a variety of ways. In one approach, the signals drive display segments in a display device, such that the output appears as a bar graph display. This display is arranged such that the segments are in order of lesser valuable to more valuable targets. When a target is present, it illuminates display segments up to and including the segment corresponding to the matching window. As described further below, a number of output devices may be used to convey the matching phase window to the user.
Additional features of the invention will become apparent with reference to the following description and accompanying drawings.